The present invention relates to a semiconductor memory device in which a large number of memory cells are divided into blocks.
In recent years, it has been shown that a semiconductor memory device can have its capacity increased from 16 kbits, 64 kbits and 256 kbits to 1 Mbits. However, as the capacity of a semiconductor memory device increases, the time required for testing it also increases. For example, if the time for testing a 16 kRAM is 1, the time for testing a 64 kRAM is 4 and the time for testing a 256 kRAM is 8. In addition, the manufacturing yield of such memory devices is low and, accordingly, the number of defective devices is much larger than the number of good devices. Therefore, the time required for testing all the devices, including defective devices, is very large, which makes the manufacturing cost high.
On the other hand, in a large capacity semiconductor memory device, such as a 64 kRAM, a plurality of memory cells are divided into blocks, which allows decoders to be simple and small in electrical structure. In this case, addresses are allocated commonly to each of the blocks. Therefore, the operation of selecting one memory cell within all of the memory cells is performed by selecting one memory cell within each of the blocks and by selecting one block within the blocks.
When testing a semiconductor memory device in which a plurality of memory cells are divided into blocks, which testing is the same as that in a semiconductor memory device without having such blocks, definite test data, such as "1", is written into each of the memory cells. In this state, the test data stored in each of the memory cells is read out and checked as to whether the read-out data is "1". However, in this case, the read operation must be repeated by the total number of memory cells and, in addition, the write operation must also be repeated for the number of memory cells. As a result, it takes a long time to test a semiconductor memory device in which memory cells are divided into blocks.